Field of Invention
The present invention relates to a lateral double diffused metal oxide semiconductor (LDMOS) device and a manufacturing method thereof; particularly, it relates to such an LDMOS device having a reduced conduction resistance and a manufacturing method thereof.
Description of Related Art
FIG. 1 is a schematic diagram showing a cross-section view of a prior art lateral double diffused metal oxide semiconductor (LDMOS) device 100. As shown in FIG. 1, the LDMOS device 100 includes: a P-type substrate 101, a drift region 102, an isolation oxide region 103, a drift oxide region 104, a body region 106, a drain 110, a source 108, and a gate 111. The drift region 102 is formed on the P-type substrate 101, and has a conductive type of N-type. The isolation oxide region 103, which is shown to be a local oxidation of silicon (LOCOS) structure, defines an operation region 103a which is a major active region for the operation of the LDMOS device. The gate 111 overlays part of the drift oxide region 104. In order to increase a withstand voltage of the LDMOS device 100 as a power device, the drift oxide region 104 has a considerable thickness. However, this increases the conduction resistance of the LDMOS device 100, so the operation speed and hence the performance of the LDMOS device 100 are decreased. Besides, a parasitic NPN transistor formed by the N-type source 108, the P-type body region 106, and the N-type drift region 102 also limits the operation speed and the performance of the LDMOS device 100.
In view of above, to overcome the drawbacks in the prior art, the present invention proposes an LDMOS device and a manufacturing method thereof, wherein the conduction resistance is reduced, and the parasitic NPN transistor is suppressed.